V850
V850 is the trademark name for a 32-bit RISC CPU architecture of Renesas Electronics for embedded microcontrollers, introduced in the early 1990s by NEC and still being developed as of 2018.
V850 Family has been evolved by many microarchitecture extensions until today, but all the extensions have binary code level backward compatibility of programs across a quarter century. Its basis is 32 of 32-bit general-purpose registers with load/store architecture. It has high code efficiency because most of frequently used instructions are mapped into 16-bit half-word.
In its earlier stage, it mainly focused on ultra-low power consumption such as 0.5 mW/MIPS. V850 has been widely used in variety of applications including: optical disk drives, hard disk drives, mobile phones, car audio and inverter compressors for air conditioners. But today, new microarchitectures are mainly toward high performance and high reliability with such as dual-lockstep redundant mechanism for automotive industry. Nowadays, V850 Family and RH850 Family are comprehensively used in a car.
Overview
The V850 is the trademark name for a 32-bit RISC CPU architecture for embedded microcontrollers of Renesas Electronics Corporation. It was originally developed and manufactured by NEC Corporation in the early 1990sas a branch of the V800 Series
and still being evolved until today.
Its base-architecture is succeeded by the variants named V850E, V850E1, V850ES,
V850E1F, V850E2, V850E2M, V850E2S, and the CPU cores.
Many compilers and debuggers are available from various development tool vendors.
Real-time operating systems are provided by compiler vendors.
In-circuit emulators are provided by many vendors. Legacy prove pod based type, the JTAG based the N-Wire interface with the N-trace type, and the Nexus interface with the Aurora Trace type, are available.
Application systems
The first V850 CPU core was used for many DVD drives manufactured by NEC Corporation, then Sony Optiarc.NEC Electronics itself intensively developed application-specific standard products for optical disk drives named SCOMBO® Series.
This first generation of processor core was also used for hard disk drives manufactured by Quantum Corporation.
The V850/xxn product line, started with V850/SA1
and V850/SV1
expanded its application to ultra-lo-power products such as "handy camcorders."
It has main and sub internal oscillator amplifier working from 1.8 V to 3.6 V with external resonator, such as crystal and ceramic.
Software STOP mode, which internal watch timer operates with 32.768 kHz sub-oscillator, consumes typically 8μA of electrical current only.
NEC also launched V850/SB1
for car audio with IEBus controller in 1998, which is ultra-low power and ultra-low noise 5 V product.
And V850/SC1
was also for "car audio".
These strategical product line expansion well succeeded to enlarge the number of sold devices.
This first generation of V850 core is also used for some NEC's mobile phones.
It is also used for the programmable host CPU of some small form factor "GSM/GPRS with GPS" embedded modem modules.
In the next phase, NEC targeted the automotive industry with a CAN bus controller on V850
as V850/SF1 at last.
The automotive industry became the main target of V850 and RH850 later on.
The V850E core targeted SoC as well as standard products,
used for some Japanese domestic mobile phones, including Sony Mobile's and NEC's.
V850E and V850ES are also used for air conditioning inverter compressors.
At this stage, one of mass market was car audio.
The V850ES core succeeded low power embedded product line,
which is ISA compatible with V850E.
NEC Electronics adopt V850 CPU core for its "USB 3.0" controllers.
Around 2005, feasibility study for "FlexRay" controller on V850E platform had been started in several companies. Yokogawa Digital Computer developed evaluation board named GT200; with a V850E/IA1 and a FPGA, which employs "FlexRay" controller developed by Bosch.
The V850E2 core primary targeted automotive areas,
but was also used for NEC's mobile phones.
Current V850 Family line up covers mainly automotive applications as well as "inter equipment connectivity" and "motor-control" specific MCUs.
The V850 Family and the RH850 Family are used in automotive industry comprehensively.
Trademark strategy
The V850 is a trademark but not a registered trademark.NEC once applied it to the Japan Patent Office, but it was rejected for registration,
as it was a natural extension of the series number.
But this action has enough effect to prevent some other people or organization registering it as the trademark. In addition Renesas has been using the V850X/xxn type trademark, such as V850E/MA1, for more than 20 years, because the combination of 1 alphabet with 2 numerical string can not be granted as the "registered" trademark. So, it is free to use without any registrations, and no one can blame it.
One exception is V850E/PHO3 .
Another usage of PHOENIX 3 of Renesas Electronics is the COOL PHOENIX 3, which employs ARM Cortex-M0 core.
By the way, "PHOENIX 3®" is the registered trade mark name of The 3DO Company as USPTO Reg. 2,009,119.
According to the current Renesas Electronics' documentation, at least the following strings are insisted as its trademark. "V800 Series," "V850 Family," "V850/SA1," "V850/SB1," "V850/SB2," "V850/SF1," "V850/SV1," "V850E/MA1," "V850E/MA2," "V850E/IA1," "V850E/IA2," "V850E/MS1," "V850E/MS2," "V851," "V852," "V853," "V854," "V850," "V850E," and "V850ES."
Because the V850 trademark has been used for more than 20 years, most people does not know that the RH850 Family is based on an extension of the V850 instruction set architecture, and has backward compatibility with V850, V850E, V850ES, and V850E2. The RH850 is thought as a new face without huge legacy software assets of V850.
Architecture
Basic architecture
The basis of V810 and V850 is a typical general-purpose registers-based load/store architecture.They have 32 of 32-bit general-purpose registers, and R0 is fixed as Zero Register which contains always zero.
In V850, R30 is implicitly used by SLD/SST; 16-bit short format load/store instructions as element pointer ,which addressing mode comprises base address register ep and immediate operand offsets.
In V850E or later microarchitectures, R3 is also implicitly used by PREPARE/DISPOSE; call stack frame creation and unwinding instructions, as stack pointer. Compilers' calling convention also uses R3 as the stack pointer.
Original V850 has simple 5-stage 1-clock pitch pipeline architecture.These are the significant feature of RISC; reduced instruction set computers. But object code size is about the half of that of MIPS R3000. because V810 and V850 adopted 16-bit and 32-bit 2-way form length instruction format respectively,
and the most of frequently used instructions are mapped into 16-bit half-word. In other words, 16-bit external bus width is relatively enough to provide instructions continuously without pipeline stalling, which enables low power consumption on the application board, and is suitable for mobile equipments. This concept is similar to Renesas SH, ARM Thumb, and MIPS16 instruction set architectures.
In addition, implementing instruction set is cautiously selected. For example, function call with Jump and Link instruction, which save next PC on a register, is also one of RISC technique to reduce the number of instructions. Return from the function can be done by jmp instruction. Typical CISC processors use call & return instructions and push the next PC on their stack memory area.
But V810 and V850 have some microarchitecture differences. V810 adopts microprogram operation method for some instructions; floating-point arithmetic and bit string operations, while V850 is a hundred percent hardwired control method. As the result, for example, the first V850 does not have floating-point arithmetic and bit manipulation instruction sets; including the "find first one/zero", except for "set/clr/negate a bit". Those extended instruction sets are revived in V850E2x extensions.
Though V800 Series adopts RISC instruction set architecture, their assembly language is hand-coding friendly. They adopt straight forward load/store architecture. In addition, the "interlock" mechanism both for the data hazards and for the branch hazards are implemented, in other words, assembly language programmer does not need to consider any delay slots. 32 general-purpose registers provide flexibility for assembly language users. Mixture of hand-assembled codes and C language compiled codes is available by using compiler options, such as "-mno-app-regs" in Gnu Compiler Collection.
It is a little bit pity that IN instruction of V810 is removed from the first V850, which enables unsigned-load from memory-mapped I/O.
Detailed discussion is available in some old journals.
Main purpose of the modification of V810 to V850 is saturation arithmetic because of customers' request.
Microarchitecture extension
V850 Series repeated many microarchitecture extension, but all the extensions have backward compatibility.In other words, all the old binary software assets, including written in a quarter century ago, work on every new core.
In addition, each microarchitecture has circuit implementation variants and fabrication process technology variants across a quarter century.
In 1996, V853 was announced as the first 32-bit RISC microcontroller with integrated flash memory.
But its maximum number of "erase and write" cycles were 16 counts.
In 1998, NEC strategically started to expand V850 product line both in standard and ASSP business and in ASIC and SoC business.
The first generation of V850 does not have unsigned load instructions, which was removed from V810, then it was added again as LD.HU and LD.BU in the second generation; V850E Series. In addition, V850E has some other user-friendly CISCy extensions such as "call table," "switch," and "prepare/dispose".
In 2001, NEC launched V850ES core, which is ultra-low-power series, but is ISA compatible with V850E.
Around 2001, Java Acceleration IP core for V850 seemed to be provided to some customers as SoC,
but detailed information is in some patents only.
In 2005, NEC Electronics introduced V850E2 core as V850E2/ME3 product line with super-scalar architecture.
In 2009, NEC Electronics introduced V850E2M as dual-core with 2.56MIPS/MHz and 1.5 mW/MIPS.
In 2011, Renesas disclosed SIMD extension for V850 as V850E2H.
As for SIMD extension, some academic studies were done.
But architectural documentation for this latest product line is disclosed to automotive customers only. It can not be found on Renesas' web site.
Its name seems to be changed to V850E3 or G3H. The only way to know about its instruction set is to do "reverse engineering" from the GNU Compiler Collection.
Power consumption
The original V810 and V850 CPU architecture is designed for ultra-low power applications.Detailed description of the V810 is described in some journals.
According to Renesas's documentation, power consumption of V850ES/Jx3-L implementation is about 70% of ARM Cortex-M3.
The V810 operates at from 2.2 V to 5.5 V with 5 V 0.8 μm fabrication process,
which power dissipation with Dhrystone MIPS are 500 mW with 15MIPS and 40 mW with 6 MIPS at 5 V and 2.2 V, respectively. It is one of the most low power 32-bit microcontroller product in the early 1990s. This specification can be achieved both by well considered instruction set architecture and by precisely tuned 5-stage 1-clock pitch pipeline microarchitecture, both of them are the benefit of the simplified RISC feature.
This ultra-low power DNA is succeeded by V850/Sxn product line, those are still alive in mass production over 20+ years. Most of them are produced with 3.3 V with 0.35μm fabrication process, which CPU core is precisely tuned to operate from 1.8 V to 3.6 V, working at 32.768 kHz to 16.78 MHz with internal oscillator amplifier plus external resonator.
Its power dissipation is 2.7 mW/MIPS for 3.3 V 0.35 μm fabrication process, and 3.6 mW/MIPS for 5 V 0.35 μm fabrication process. "Software STOP" stand-by mode for mask ROM version of V850/SA1, which internal watch timer operates at 3.3 V with 32.768 kHz sub-oscillator, consumes typically 8 μA electrical current only. And, Subclock normal operation mode at 3.3 V with 32.768 kHz consumes 40 μA typically, 140 μA at the maximum.
Its 1.8 V typical CPU operation current at 32.768 kHz might be 22 μA, which power dissipation should become 40 μW. It corresponds to 1.0 mW/MIPS.
The V850/Sxn product line is also tuned for low noise both with EMI and with EMS. Especially, V850/SB1 and SB2 are specially tuned for low EMI noise with 5 V internal voltage regulator, which enables high sensitivity of receiving RF for car radio.
In 2011, NEC launched 3rd generation microarchitecture V850ES ultra-low-power series, which insists 1.43 mW/MIPS at operating voltage range from 2.2 V to 2.7 V,
but this first implementation of V850ES microarchitecture seems to be incomplete compared with later generations of the same architecture.
Its "Sub-IDLE" stand-by mode for mask ROM version of V850ES/SA2 and V850ES/SA3, those internal RTC operate at 2.5 V with 32.768 kHz sub-oscillator, consume typically 5 μA electrical current only. But, Subclock normal operation mode at 2.5 V with 32.768 kHz consume 40 μA typically, 100 μA at the maximum.
Its 2.2 V typical CPU operation current at 32.768 kHz might be 31 μA, which power dissipation should be 68 μW. It is about 1.7 times of V850/SA1. It corresponds to 1.6 mW/MIPS.
The V850ES/JG3-L product line has ultra-low power variants, named μPD70F3792, 793 and μPD70F3841, 842. They can operate from 2.0 V to 3.6 V with 18 μA typical electrical current at 32.768 kHz, which should be 22 μW at 2.0 V. It corresponds to 0.52 mW/MIPS. In addition, their sub-clock idle mode, with watch timer, power consumption should be typically 3.4 μW at 1.8 V.
The power consumption of NA85E2 core is much larger compared with NU85E core in the same CB-12L
fabrication process.
The reason is that V850E2x core has 128-bit width instruction prefetch bus and plural of Instruction Prefetch Queues,
while average instruction length of V800 Series is almost 16-bit.
It means 16 instructions are possibly fetched from the memory at once, then the memory and the prefetcher circuits sleep rest 3 to 7 cycles for dual-pipeline superscalar architecture.
This gap enlarges electrical current amplitude differences.
In addition, the peak electric current exceeds allowance for the voltage stabilizers of mobile gadgets.
As for V850E2M CPU core, it is publicly introduced as 1.5 mW/MIPS, 3 times of former generations, although it should have advantages of new fabrication process technologies.
Some mobile equipment avoids using dual-instruction execution, in other words, adopting the single-instruction execution setting to reduce electrical current amplitude differences.
Development methodology
Because the V850 Familyis developed as a branch of V800 Series,
the basic CPU architecture is inherited from V810.
Instruction set architecture of the first V850 is drastically modified from that of V810, but the difference is within a patch level from GNU Compiler Collection point of view. The main purpose of this change is to implement saturation arithmetic by customers' request.
Detailed design methodology of V810 is described in a journal.
V850 utilizes this design assets. But datapath logic was changed from dynamic logic to static logic, to enable 32.768 kHz real-time clock frequency operation mode.
The register-transfer level "CPU architecture design" of the V810 is developed with the Functional Description Language
on the Falcon Simulator software, those are NEC's CAD tools.
This methodology is the same as that of NEC V60.
In the late 1980s, the Verilog HDL has not acquired by Cadence Design Systems yet.
The FDL had been used until the middle of the 2000s, and was also used for the development of NEC's super-computer; named Earth Simulator.
The difference from V60 is that the circuit diagram was written with schematic editor, not of Calma, but of Mentor Graphics called NETED,
a part of the Design Architect product
on Apollo Computer's workstation, which is the most major schematic editor at that moment.
It enabled to generate netlists, such as EDIF and SPICE, for LVS program like cadence's Dracula products, and NEC's and Zycad netlist for logic simulation. Later on, this circuit diagram of NETED became able to generate gate-level Verilog HDL netlist for V850.
Most of the register-transfer level FDL netlist was translated to the gate-level schematic by hand, because the logic synthesis has not yet to be practical use at that moment.
The FDL was divided into datapath and random logic precisely. For the datapath part,
the gate-level circuit diagram enabled manually repeated artwork. On the other hand, for the random logic part, logic synthesis was tried to use for generating gate-level schematic, but it was about 10% of the total circuit.
In addition, formal verification has also not to be practical use yet, which means full regression test by dyamic logic simulation is required for gate-level netlist to compare with RTL one. For gate-level logic simulation, NEC's CAD tool named V-SIM is usually used.
But sometimes hardware emulator, such as Zycad LE simulation accelerator,
is used for this purpose.
Instruction opcode table
Each opcode table is from User's Manual: Architecture.V810 (obsoleted)
- 1st map opcodes
V850 (1st Gen.)
- 1st map opcodes
- 2nd map opcodes
V850E/E1/ES
- 1st map opcodes
- 2nd map opcodes
List of the ''V800 Series'' CPU cores
| CPU core | Product variants | GCC targeting options | Remarks |
| V810 | V810 Family | Revert patch required. Available on Planet Virtual Boy. GCC named gccVB. | Obsoleted products. Unsigned & signed load. μcoded float 5-stage pipeline. 6.7 mW/MIPS |
| V810 | V830 Family | ditto | Obsoleted products. High end products. Multimedia extension. |
| V850 | V850 Family started V851 — V852 V853, V854 | none or -mv850 | Obsoleted products. 5-stage pipeline. 4.4 mW/MIPS |
| V850 | V850/xxn | none or -mv850 | Not for new developments. Signed load. 1.15 Dhrystone MIPS/MHz Ultra-low power products. 3.6 mW/MIPS 2.7 mW/MIPS 1.0 mW/MIPS |
| V850E | V850E/MS1, V850E/MS2 | -mv850e | Not for new developments. Unsigned & signed load. 1.3 Dhrystone MIPS/MHz Standard products. |
| V850E1 | V850E/xxn NB85E SoC core NU85E SoC core | -mv850e1 or ‑mv850es | Unsigned & signed load. N-Wire and N-Trace. Standard products. SoC Products. |
| V850ES | V850ES/xxn | -mv850es or ‑mv850e1 | Unsigned & signed load. Ultra-low power products. 1.43 mW/MIPS 0.52 mW/MIPS Shift to V850E2S requested. |
| V850E1F | V850E/PH2, V850E/PH3 V850E/PHO3 | Patch required. | H/W float. |
| V850E2 | V850E2/ME3 NA85E2 SoC core | -mv850e2 | Not for new developments. Many errata but still alive. Single insn. executing. 7-stage pipeline. S/W float. Standard Products. SoC Products. |
| V850E2 | V850E2/xxn NB85E2 SoC core | -mv850e2 | Errata cleaned up. Dual instruction executing. 7-stage pipeline. S/W float. Standard Products. SoC Products. |
| V850E2M G3 | V850E2/xxn RH850/nxn | -mv850e2v3 and -msoft-float | S/W float. Dual instruction executing. 7-stage pipeline. 2.56 Dhrystone MIPS/MHz 1.5 mW/MIPS Multi CPU core support. Memory Protection. |
| V850E2R G3R | V850E2/xxn RH850/nxn | -mv850e2v3 | H/W float. Dual instruction executing. 7-stage pipeline. 2.56 Dhrystone MIPS/MHz Multi CPU core support. Memory Protection. |
| V850E2S G3K | V850E2/xxn RH850xnx | -mv850e2v3 and ‑msoft‑float | S/W float. 5-stage pipeline. 1.9 Dhrystone MIPS/MHz Multi CPU core support. Memory Protection. Ultra-ultra-low power. Standard products. V850ES/xxn pin compat. Automotive products. Shift to RH850 requested. |
| V850E2H V850E3 G3M G3MH, G3KH | RH850/xnx | -mv850e2v4 and ‑mloop or -mv850e3v5 and ‑mloop | SIMD extension. 64-bit multiple load/store. Loop extension. H/W float. Memory Protection. Multi CPU core support. Automotive products. |
SoC solutions
SoC IP cores
In 1998, NEC started to provide V850 Family as an ASIC core to expand its ASIC business.In addition, both the V850E1 CPU core named Nx85E
and the V850E2 CPU core named Nx85E2,
respectively, are also used for expanding its standard products business with ASIC design methodology.
Various SoC utilize this core. For example, in 2003, Dotcast, Inc. used NU85E core for a set top box receiver of the digital datacasting based on dNTSC method. This core is fabricated with CB-10 0.25μm process technology which adopts 5 layered metal.
The NA85E2C core, which is developed in 1.5 V 150 nm CB-12L
fabrication process,
has many errata.
But it seems not to be a matter for uses, because this is long-running product.
NEC also expanded the core for 130 nm CB-130 fabrication process
cell-base IC, but it is unclear.
Synopsys DesignWare® IP core for V850E was once announced, but support obsoleted.
| Name | Core | Cell-base series | Power supply | Node/ Gate L | Fab. proc. | Freq. MHz | Type | ICE | Docs. |
| NA851C | V851 | CB-9VX | 3.3 V | 350 nm | UC1 | 33 | With peripheral | ||
| NA853C | V853 | CB-9VX | 3.3 V | 350 nm | UC1 | 33 | With peripheral | ||
| NA85E | V850E1 | CB-9VX | 3.3 V | 350 nm | UC1 | Bulk core | |||
| NB85E | V850E1 | CB-9VX | 3.3 V | 350 nm | UC1 | 66 | Bulk core | ||
| NB85ET | V850E1 | CB-9VX | 3.3 V | 350 nm | UC1 | 66 | w/ Trace I/F | ||
| NB85E | V850E1 | CB-10 | 2.5 V | 250 nm | UC2 | 66 | Bulk core | ||
| NB85ET | V850E1 | CB-10 | 2.5 V | 250 nm | UC2 | 66 | w/ Trace I/F | ||
| NU85EA | V850E1 | CB-10VX | 2.5 V | 250 nm | UC2 | 100 | Bulk core | ||
| NU85ET | V850E1 | CB-10VX | 2.5 V | 250 nm | UC2 | 100 | w/ Trace I/F | ||
| NDU85ETV14 | V850E1 | CB-12L | 1.5 V | 150 nm/ 130 nm | UX4L | w/ Trace I/F | |||
| NDU85ETVxx | V850E1 | CB-12M | 1.5 V | 150 nm/ 130 nm | UX4M | w/ Trace I/F | |||
| NA85E2C | V850E2 | CB-12L | 1.5 V | 150 nm/ 130 nm | UX4L | 200 | w/ Trace I/F | ||
| NB85E2C | V850E2 | CB-12L | 1.5 V | 150 nm/ 130 nm | UX4L | 200 | w/ Trace I/F | ||
| V850E2x | CB-130L | 1.2 V | 130 nm/ 95 nm | UX5L | Replaced by ARM946 | ||||
| — | — | CB-90L | 1.2 V | 90 nm/ | UX6L | Replaced by ARM946. | |||
| In-house | V850E2x | UX6LF | 1.2 V | 90 nm/ | UX6LF | Renesas internal use only ??? | |||
| — | — | CB-65L | 1.2 V | 65 nm/ | UX7L | Skipped. Replaced by ARM1156. | |||
| — | — | CB-55L | 1.2 V | 55 nm/ 50 nm | UX7LS | Skipped. Replaced by ARM Cortex-M3. | |||
| — | — | CB-40L | 1.1 V | 40 nm/ 40 nm | UX8L | Replaced by ARM Cortex-M4. | |||
| In-house | V850E3 | RV40F | 1.1 V | 40 nm/ 40 nm | RV40F | 320 | Renesas internal use only ??? |
FPGA prototyping systems for SoC
systems for V850E1, V850E2, and V850E2M core based SoC were intensively developed to expand SoC business. They comprised a V850 CPU core LSI board and "FPGA add-on"s. Most of SoC products were for mobile equipments; because the power dissipation of original V800-Series RISC architecture was much lower compared with CISC.It is the same logic as the ARM architecture is widely used for mobile gadgets.
†TEG: Test Element Group
- Renesas : COREBEST
- Renesas : Microssp
- Renesas : Hybrid Emulator
- Renesas : PFESiP® EP1 Evaluation Board
- Renesas : PFESiP® EP1 Evaluation Board Lite
- Renesas : PFESiP® EP3 Evaluation Board : V850E2M CPU core, max. 266 MHz operation
- Xylon: logicBRICS
Strategic confusion
but this high-pace expansion brought much confusions. For example, some of V850E2/xxn products have already been requested to replace with RH850/xnx as of 2018.
It may be, or may not be, the Product Longevity Program point of view.
In addition, in 2012 Renesas intensively started to promote the migration from 10 years old V850ES/Jx3 product lines to newly produced V850E2/Jx4, such as for Ethernet and for USB,
but the newer products are not listed on their web site as of 2018.
Currently, Renesas Electronics is designing "dual" lockstep system, but its predecessor NEC V60-V80 had "multiple modular" lockstep mechanism called FRM
either with roll-back by "retry" or with roll-forward by "exception" for each fault detected instruction in more than 20 years ago.
In addition, NEC V60-V80 has plural of implementation of UNIX System V port product releases, one of which is real-time UNIX RX/UX-832
. Its multiprocessor implementation is called MUSTARD, which works 8 processors at the maximum simultaneously, and their lockstep mechanism was dynamically configurable.
Now, where are these technologies ?
In 2001, both NEC Corporation and Synopsys, Inc. announced they agreed to promote V850E as DesignWare® IP core.
But as of 2018, the V850E is not listed on DesignWare libraries.
Lucent Technologies and Texas Instruments once licensed V850 and V850E SoC core, respectively,
but the device can not be found.
Metrowerks once developed CodeWarrior compiler for V850, which was one of the major compiler provider of V850 in 2006.
But around 2010, they discontinued it after absorption by Motorola's semiconductor sector in 1999, Freescale Semiconductor in 2003, currently NXP Semiconductors from 2015.
In 2006, NEC did not show any roadmap for the V850 Family as SoC cores. The V850E2 core, developed in 2004, described as if the last core for SoC. Instead of that, NEC introduced ARM9 and ARM11, especially for mobile equipments.
But this corporate decision suddenly decreased both the net profit of LSI devices, because of the royalty for ARM and of the price competition with other ARM SoC providers. The sales revenue of the "V850 total solutions," such as development tools, real-time OS, middle-ware packages, and in-circuit emulators, also decreased. The number of sold V850 device count was also suddenly decreased because mobile equipments were the major customers of V850E1 and V850E2 cores at that moment.
In 2009, NEC Electronics merged with Renesas Technology Corp.
In 2008, KMC, which is one of the major and of the first provider of in-circuit emulator for V850 Family, announced exeGCC updating from Rel. 3 to Rel. 4,
but it excluded V850 form this updating list, although PowerPC and ARM v7 was newly added. It chose SH-4A and ARM v7 instead of V850 and RH850
though it had been tightly worked with NEC and Renesas Electronics.
The V850 CPU cores run uClinux,
but on October 9, 2008, Linux kernel support for V850 was removed in revision 2.6.27., because NEC stopped the maintenance.
The person in charge of V850 Linux kernel maintenance was moved from NEC to Renesas by its merger, but his job was still compiler design and never returned to Linux kernel maintenance.
This corporate decision prevent the porting possibility for Android.
Regarding the Linux kernel support as of 2018, Renesas Electronics mainly focuses on SH3/SH4 and M32R processors.
Target software solutions
Libraries
- Red Hat, Inc.: The Newlib for C runtime library and mathematical lirary
- Micro Digital Inc.: GoFast® for NEC V85x Fast Software Floating Point Library
- The GNU Compiler Collection: Software floating point
- The GNU Compiler Collection: Decimal floating point
Operating systems
Some of operating systems require the Memory Protection Unit to divide tasks strictly for reliability and safety reasons. In such cases, v850e2v3 microarchitecture or above are required.
ITRON based real-time OS
ITRON is an open standard specification of real-time OS, which is major in Japan.Its specification is defined under leadership of Ken Sakamura as a part of TRON project. Initial letter I stands for "Industrial." Because ITRON specification defines interface and skeleton only, each vendor has its own taste of implementation.
- Renesas:
- *RI850MP Real-time OS for V850E2M Dual Core
- *RI850V4 V2 Real-time OS for RH850 Family
- *RI850V4 V1 Real-time OS for V850 Family
- Toppers Project: Open source TOPPERS/JSP
- A.I. Corporation: Toppers-Pro/xxx
- T-Engine Project: Open source T-Kernel by TRON Forum
- eSOL: eT-Kernel; Extended T-Kernel — RTOS for embedded systems
- *eT-Kernel/Compact, eT-Kernel/Embedded, eT-Kernel/POSIX
- *eT-Kernel Multi-Core Edition
- eCos: Open source real-time operating system
AUTOSAR, OSEK/VDX compliant real-time OS
In Japan, this research was started in 2006 as a joint project by JAIST and DENSO. Renesas Electronics joined this project in 2009.
Because the current RH850 and V850 processors are principally targeted at the automotive industry, it is one of a strategical product of Renesas Electronics. However, its documentation is only available in Japanese as its main customer is Toyota Motor Corporation.
- Renesas: RV850
- ETAS GmbH: RTA-OS RH850/GHS, RTA-OSEK V850E/GHS
- Mentor Graphics : Nucleus OSEK
- HighTec EDV-Systeme GmbH: EB tresos Safety OS
- Toppers Project: Open source TOPPERS/AUTOSAR
- eSOL: eMCOS AUTOSAR profile''
Other real-time OS
- SYSGO AG:
- *PikeOS; Embedded Virtualization Hypervisor
- eSOL:
- *eMCOS; Scalable RTOS, Distributed Microkernel Architecture, non-hypervisor type OS
- MiSPO:
- *NORTi Professional; Real-time OS + TCP/IP stack + Simulator
- SEGGER
- *embOS V850 NEC, embOS V850 Green Hills, embOS V850 IAR
- Wind River Systems:
- *VxWorks®: Ported in the early 1990s.
The Tornado® IDE is stated that MP licenses has been sold via NEC in 2000, currently Renesas. - Mentor Graphics :
- *Nucleus PLUS
Linux
- uCLinux
- Linux kernel
Middleware packages
- Renesas: SD Memory Card Control
Software development tools
Compilers and assemblers
Most of the compilers, both for the V850 Family; and for the RH850 Family, are exactly the same product, and extended ISA targets are controlled by "command line options."Compilers for the V850 Fmily and the RH850 Family include:
- The GNU Compiler Collection developed both:
- * by "Red Hat, Inc." as a part of the GNUPro Developers Kit
- * by "KMC " as a part of the exeGCC
- * by "CyberTHOR Studios, Ltd.": Free pre-built binaries can be downloaded by registration.
- Renesas:
- *C Compiler Package for V850 Family
- ** CA850 C compiler for V850E1 and V850ES
- ** CX C compiler for V850E2M and V850E2S
- *Software Package for V850 for V850E2
- *CC-RH C compiler package for G3, G3K, G3M
- GHS : The Green Hills Optimizing Compilers
- Wind River Systems: Diab Compiler
- IAR Systems: Embedded Workbench
- Altium Limited: Tasking®; RENESAS RH850 SOFTWARE DEVELOPMENT TOOLS
- HighTec EDV Systeme GmbH: HighTec Development Platform
- GAIO Technology: XASS-V Series cross development tools
- Metrowerks: CodeWarrior''
Disassemblers
- Radare2: Radare2 is a set of command-line programming tools for reverse engineering. Open-source code is available from GitHub repository.
- IDA Pro: IDA Pro is a freeware disassembler for hobby use. A plugin for V850 is available. Download site is gray for securities.
GUI based debuggers
- Renesas:
- *ID850: For the combination of CA850 compiler and SM850 instruction set simulator.
- *ID850NW: For the combination of N-Wire based in-circuit emulators.
- *ID850QB: For the combination of probing-pod based emulator IEQUBE2
- NDK : Operation started in 1950 as subsidiary of NEC.
- *NW-V850-32
- GHS : Multi: General-purpose debugger.
- Red Hat, Inc.: Insight : GUI front-end tightly combined with GNU Debugger.
- Mentor Graphics : code|lab Developer Suite
- By N-Wire based in-circuit emulator vendors:
- *KMC and Midias Lab.: PARTNER
- *Sohwa & Sophia Technologies:WATCHPOINT
- *DTS INSIGHT : microVIEW-PLUS
- *Computex: CSIDE
Instruction set simulators
- Renesas: SM850
- Open Virtual Platform: Instruction set simulator
- Synopsys: VDK for Renesas RH850 MCU
Automated code reviewers
Dynamic code analyzers with simulators
- Renesas: TW850
- Renesas: AZ850
- Gaio Technology: Coverage Master winAMS
Static code analyzers
- GHS : DoubleCheck ISA tool
- Rogue Wave Software, Inc: Klocwork
IDE (Integrated Development Environments)
- Renesas: CS+
- GHS : Multi
- Eclipse Plugins
- *GNU Compiler Collection and GNU Debugger
- *Wind River Workbench
Hardware development tools
ICE (In-circuit emulators)
Most of in-circuit emulators, such as Rnesas IE850can be used both for V850 Family and for RH850 Family, but may require firmware updating.
The latest "trace function" of the JTAG based in-circuit emulator is replaced from the N-Trace
to the Aurora Trace.
Full probing pod type
Full probing pod type in-circuit emulator is sometimes called as full ICE or legacy ICE.- Renesas IE850
- Naito Densei Machida Mfg. Co., Ltd.
- *Asmis brand for custom LSIs.
ROM emulator type
- Lauterbach: ROM Monitor for V850
- KMC : PARTNER-ET II
JTAG N-Wire and N-Trace type
is a JTAG-based debugging interface specification, which circuit implementation is called TAP Controller,
primarily compiled by Philips N.V. about a quarter century ago. But it is perhaps not disclosed publicly in its earlier stage. As the result, each semiconductor and in-circuit emulator vendor implemented similar interfaces independently. Nowadays, it is standardized by IEEE 1149.1 Working Group.
- Renesas
- *E1 Emulator: USB 2.0 based affordable compact housing equipment.
- *PCMCIA N-Wire Card IE-V850E1-CD-NW
- Naito Densei Machida Mfg. Co., Ltd. : Asmis brand.
- Midas Lab.: RTE-2000H with PARTNER debugger
- Lauterbach: Trace32
- IAR Systems
- DTS INSIGHT : adviceLUNA II
- Computex: PALMiCE3 V850
- Sohwa & Sophia Technologies: Universal Probe Blue with WATCHPOINT debugger
- KMC : PARTNER-Jet
Nexus and Aurora trace type
Aurora is a high speed signal transfer specification. Its data link layer communications protocol is a point-to-point serial links, and physical layer is a high speed differential signaling.
- Lauterbach: Trace32: PowerTrace for NEXUS
Flash ROM programmers
Gang writers (gang programmers)
A gang writer, or a gang programmer, is an old terminology for programmable ROM writers, or programmers. Its name origin comes from that it steals the binary code from one device, and write it to plural ones simultaneously. This read device is sometimes called as a master device. For mass production use, a dedicated attachment board with "a set of sockets," i.e. "a gang," is needed. As usual, instead of a programmed master device, an object code file can be copied from a PC via download cable, or from a USB stick. Most of gang writers accept ASCII format files such as Intel HEX and Motorola SREC, or binary format files such as ELF.This method is suitable for mass production.
- TESSERA Technology Inc.: Stick GANG Writer
Programming service providers
- Minato Holdings, Inc.
On board programming with ICE
May be or may not be IEEE standard 1532-2002; a standard for in-system configuration of programmable components.
Direct connection via RS-232C
If the target board has a RS-232C connector and a transceiver IC, such as ICL32xx,for the UARTx peripheral function of V850 device, flash ROM programming with directly connected PC might be available.
The Renesas Flash Programmer software V2
or V3
is required.
Dedicated on board programmer
On board programming is also available via UARTx or CSIx+HS peripheral on V850 devices by using dedicated programmer hardware.- Renesas: PG-FP6
Ancient PROM writers
and V852, an ancient PROM programmer with dedicated adapter is required.
- Renesas PG-1500
Gray zone tools