Standard Delay Format
Standard Delay Format is an IEEE standard for the representation and interpretation of timing data for use at any stage of an electronic design process. It finds wide applicability in design flows, and forms an efficient bridge between dynamic timing verification and static timing analysis.
It was originally developed as an OVI standard, and later modified into the IEEE format. Technically only the SDF version 4.0 onwards are IEEE formats.
It is an ASCII format that is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.
It has usually two sections: one for interconnect delays and the other for cell delays.
SDF format can be used for back-annotation as well as forward-annotation.
See also: VITAL, EDIF
