PowerPC 400
The PowerPC 400 family is a line of 32-bit embedded RISC processor cores based on the PowerPC or Power ISA instruction set architectures. The cores are designed to fit inside specialized applications ranging from system-on-a-chip microcontrollers, network appliances, application-specific integrated circuits and field-programmable gate arrays to set-top boxes, storage devices and supercomputers.
Applied Micro Circuits Corporation bought assets concerning the 400 family cores from IBM in April 2004 for $227 million, and they now market the processors under their own name. IBM continues evolving the cores while supplying design and foundry services around the cores. Several cores are also available for licensing by OEMs from IBM and Synopsys.
Variants
PowerPC 403
Introduced in 1994, the PowerPC 403 was one of the first PowerPC processors. It was the first one targeted strictly to the embedded market. Compared to the other PowerPC processors of the era, it was at the very low end, lacking a memory management unit or floating point unit, for instance. The core was offered for custom chips and in pre packaged versions, including versions with MMU, speeds ranging from 20 to 80 MHz.The PowerPC 403 is used in, among other appliances, thin clients, set-top boxes, RAID-controllers, network switches and printers. The first TiVo used a 54 MHz PowerPC 403GCX.
AMCC acquired the design of 403 from IBM in 2004, but have chosen not to market it, instead focusing on the 405 and 440 cores.
PowerPC 401
While the 403 was popular, it was also too high performance and too costly for some applications, so in 1996 IBM released a bare bones PowerPC core, called PowerPC 401. It has a single issue, three-stage pipeline, with no MMU or DMA and only 2 KB instruction and 1 KB data L1 caches. The design contained just 85,000 transistors in all and operated at up to 100 MHz, drawing only 0.1 W or less. Applications using the 401 core range from set-top boxes and telecom switches to printers and fax machines.PowerPC 405
The PowerPC 405 was released in 1998 and was designed for price or performance sensitive low-end embedded system-on-a-chip designs. It has a five-stage pipeline, separate 16 KB instruction and data L1 caches, a CoreConnect bus, an Auxiliary Processing Unit interface for expandability and supports clock rates exceeding 400 MHz. The 405 core adheres to the current Power ISA v.2.03 using the Book III-E specification. Both AMCC and IBM are developing and marketing processors using 405 cores. IBM and Synopsys also offers a fully synthesizable core. IBM has announced plans to make the specifications of the PowerPC 405 core freely available to the academic and research community.PowerPC-405-based applications include digital cameras, modems, set-top boxes, cellphones, GPS-devices, printers, fax machines, network cards, network switches, storage devices and service processors for servers. Up to two 405 cores are used in Xilinx Virtex-II Pro and Virtex-4 FPGAs. In 2004 Hifn bought IBM's PowerNP network processors that uses 405 cores.
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; APM801xx
; POWER8 on-chip controller
PowerPC 440
Introduced in 1999, the PowerPC 440 was the first PowerPC core from IBM to include the Book E extension to the PowerPC specification. It also included the CoreConnect bus technology designed to be the interface between the parts inside a PowerPC based system-on-a-chip device.It is a high-performance core with separate 32 KB instruction and data L1 caches, a seven-stage out-of-order dual-issue pipeline, supporting speeds of up to 800 MHz and L2 caches up to 256 KB. The core lacks a floating point unit but it has an associated four-stage FPU that can be included using the APU interface. The 440 core adheres to the Power ISA v.2.03 using the Book III-E specification.
Xilinx currently incorporates one or two cores into the Virtex-5 FXT FPGA.
Both AMCC and IBM are developing and marketing stand alone processors using 440 cores. IBM and Synopsys also offers fully synthesized cores.
; BRE440 Rad Hard SOC
; QCDOC
; Blue Gene/L
; SeaStar
; AMCC 460
; Titan
; Virtex-5 FXT
; LSI SAS
; Acalis CPU872
PowerPC 450
The processing core of the Blue Gene/P supercomputer designed and manufactured by IBM. It is very similar to the PowerPC 440 but few details are disclosed.; Blue Gene/P
PowerPC 460
Introduced in 2006, the 460 cores are similar to the 440 but reach 1.4 GHz, are developed with multi-core applications in mind and have 24 additional digital signal processing instructions. The cores are designed to be low-power but high performance and the 464-H90 is expected to draw only 0.53 W at 1 GHz. The 460 core adheres to Power ISA v.2.03 using the Book III-E specification.- PowerPC 460S a completely synthesized core and can be licensed from IBM or Synopsys for manufacturing on different foundries. 460S can be configured with different amounts of L1 and L2 cache as well as with or without SMP and FPU.
- PowerPC 464-H90 a 90 nm, hard core, released in 2006, will offer a customizable core for ASICs that can be manufactured with IBM or at manufacturing facilities at Chartered or Samsung.
- PowerPC 464FP-H90 released in 2007, is a hard core that adds a double precision floating point unit.
AppliedMicro
- PowerPC 460SX and 460GTx are based on the 464-H90 core. They are targeted towards very high-end storage and networking applications, respectively. They run at 0.8 to 1.2 GHz, have 512 KB of L2 cache that doubles as SRAM storage, a 400 MHz clock DDR2 memory controller, four Gigabit Ethernet controllers, PCIe controllers and a variety of application-specific accelerators and controller facilities. They are manufactured on a 90 nm process.
- APM82181 a 0.8–1 GHz 464-based SoC designed for storage devices. DDR2-controller, 256 KB SRAM configurable as L2 cache. PCIe, SATA2, USB2, Gbit Ethernet and various other I/O interfaces and accelerators like TCP/IP offloading, and RAID5 and cryptography accelerators
- APM86190 and APM86290 PACKETpro codenamed "Mamba", they are single and dual core SoC processors based on the PowerPC 465 core, running at 0.6-1.5 GHz. 32 KB instruction/32 KB data L1 caches and 256 KB L2 cache, DDR3 controller, PCIe, SATA2, USB2, Gbit Ethernet and various other I/O interfaces and accelerators like TCP/IP offloading and a cryptography accelerator with non-volatile storage for crypto keys and secure boot and tampering detection.
- APM86791 PACKETpro codenamed "Keelback", it is a single core SoC processor based on the PowerPC 465 core running at 1 GHz with 32 KB instruction/32 KB data L1 caches and 256 KB L2 cache, DDR3 controller, 2x PCIe, 2x SATA2, 2x USB2, 4x Gbit Ethernet. It also incorporates an ARM Cortex-M3 based cryptography accelerator named SLIMpro running at 250 MHz that allows secure booting from ROM and tempering detection.
PowerPC 470
- LSI Axxia ACP3448 1.8 GHz, 4× 476FP cores, 512 kB L2 cache per core, 4 MB L3 cache on chip, 2× DDR3 controllers, 2× 10 Gbit Ethernet, 3× PCIe, and a variety of network-processing engines
- C*Core C1000 a family of 476FP-core-based embedded processors for consumer electronics
- ChinaChip CC2000 a 476FP-core-based processor with integrated DSP and GPU for game consoles
- NTC Module 1888TKh018 SoC for aircraft onboard video and multimedia processing systems