One-instruction set computer


A one-instruction set computer, sometimes called an ultimate reduced instruction set computer, is an abstract machine that uses only one instructionobviating the need for a machine language opcode. With a judicious choice for the single instruction and given infinite resources, an OISC is capable of being a universal computer in the same manner as traditional computers that have multiple instructions. OISCs have been recommended as aids in teaching computer architecture and have been used as computational models in structural computing research.

Machine architecture

In a Turing-complete model, each memory location can store an arbitrary integer, anddepending on the modelthere may be arbitrarily many locations. The instructions themselves reside in memory as a sequence of such integers.
There exists a class of universal computers with a single instruction based on bit manipulation such as bit copying or bit inversion. Since their memory model is finite, as is the memory structure used in real computers, those bit manipulation machines are equivalent to real computers rather than to Turing machines.
Currently known OISCs can be roughly separated into three broad categories:
machines are the simplest class.

BitBitJump

A bit copying machine, called BitBitJump, copies one bit in memory and passes the execution unconditionally to the address specified by one of the operands of the instruction. This process turns out to be capable of universal computation because copying bits can conditionally modify the code that will be subsequently executed.

Toga computer

Another machine, called the , inverts a bit and passes the execution conditionally depending on the result of inversion. The unique instruction is TOGA which stands for TOGgle a And branch to b if the result of the toggle operation is true.

Multi-bit copying machine

Similar to BitBitJump, a multi-bit copying machine copies several bits at the same time. The problem of computational universality is solved in this case by keeping predefined jump tables in the memory.

Transport triggered architecture

Transport triggered architecture is a design in which computation is a side effect of data transport. Usually, some memory registers within common address space perform an assigned operation when the instruction references them. For example, in an OISC using a single memory-to-memory copy instruction, this is done by triggering ports that perform arithmetic and instruction pointer jumps when written to.

Arithmetic-based Turing-complete machines

Arithmetic-based Turing-complete machines use an arithmetic operation and a conditional jump. Like the two previous universal computers, this class is also Turing-complete. The instruction operates on integers which may also be addresses in memory.
Currently there are several known OISCs of this class, based on different arithmetic operations:
Common choices for the single instruction are:
Only one of these instructions is used in a given implementation. Hence, there is no need for an opcode to identify which instruction to execute; the choice of instruction is inherent in the design of the machine, and an OISC is typically named after the instruction it uses. Each of the above instructions can be used to construct a Turing-complete OISC.
This article presents only subtraction-based instructions among those that are not transport triggered. However, it is possible to construct Turing complete machines using an instruction based on other arithmetic operations, e.g., addition. For example, one variation known as DLN has only two operands and uses decrement as the base operation. For more information see Subleq derivative languages .

Subtract and branch if not equal to zero

The SBNZ a, b, c, d instruction subtracts the contents at address a from the contents at address b, stores the result at address c, and then, if the result is not 0, transfers control to address d.

Subtract and branch if less than or equal to zero

The instruction subtracts the contents at address from the contents at address, stores the result at address, and then, if the result is not positive, transfers control to address .
Pseudocode:

subleq a, b, c ; Mem = Mem - Mem
; if goto c

Conditional branching can be suppressed by setting the third operand equal to the address of the next instruction in sequence. If the third operand is not written, this suppression is implied.
A variant is also possible with two operands and an internal accumulator, where the accumulator is subtracted from the memory location specified by the first operand. The result is stored in both the accumulator and the memory location, and the second operand specifies the branch address:

subleq2 a, b ; Mem = Mem - ACCUM
; ACCUM = Mem
; if goto b

Although this uses only two operands per instruction, correspondingly more instructions are then needed to effect various logical operations.

Synthesized instructions

It is possible to synthesize many types of higher-order instructions using only the instruction.
Unconditional branch:
; :
subleq Z, Z, c

Addition can be performed by repeated subtraction, with no conditional branching; e.g., the following instructions result in the content at location being added to the content at location :
; :
subleq a, Z
subleq Z, b
subleq Z, Z

The first instruction subtracts the content at location from the content at location and stores the result in location. The second instruction subtracts this result from, storing in this difference ; the third instruction restores the value 0 to.
A copy instruction can be implemented similarly; e.g., the following instructions result in the content at location getting replaced by the content at location, again assuming the content at location is maintained as 0:
; :
subleq b, b
subleq a, Z
subleq Z, b
subleq Z, Z

Any desired arithmetic test can be built. For example, a branch-if-zero condition can be assembled from the following instructions:
; :
subleq b, Z, L1
subleq Z, Z, OUT
L1: subleq Z, Z
subleq Z, b, c
OUT:...

Subleq2 can also be used to synthesize higher-order instructions, although it generally requires more operations for a given task. For example, no fewer than 10 subleq2 instructions are required to flip all the bits in a given byte:
; :
subleq2 tmp ; tmp = 0
subleq2 tmp
subleq2 minus_one ; acc = -1
subleq2 a ; a' = a + 1
subleq2 Z ; Z = - a - 1
subleq2 tmp ; tmp = a + 1
subleq2 a ; a' = 0
subleq2 tmp ; load tmp into acc
subleq2 a ; a' = - a - 1
subleq2 Z ; set Z back to 0

Emulation

The following program emulates the execution of a -based OISC:

int memory, program_counter, a, b, c
program_counter = 0
while :
a = memory
b = memory
c = memory
if :
program_counter = -1
else:
memory = memory - memory
if :
program_counter += 3
else:
program_counter = c

This program assumes that is indexed by nonnegative integers. Consequently, for a instruction, the program interprets,, or an executed branch to as a halting condition. Similar interpreters written in a -based language can be found in the external links below.

Compilation

There is a compiler called Higher Subleq written by Oleg Mazonka that compiles a simplified C program into code.

Subtract and branch if negative

The instruction, also called, is defined similarly to :

subneg a, b, c ; Mem = Mem - Mem
; if goto c

Conditional branching can be suppressed by setting the third operand equal to the address of the next instruction in sequence. If the third operand is not written, this suppression is implied.

Synthesized instructions

It is possible to synthesize many types of higher-order instructions using only the instruction. For simplicity, only one synthesized instruction is shown here to illustrate the difference between and.
Unconditional branch:
subneg POS, Z, c
...
c: subneg Z, Z

where and are locations previously set to contain 0 and a positive integer, respectively;
Unconditional branching is assured only if initially contains 0. A follow-up instruction is required to clear after the branching, assuming that the content of must be maintained as 0.

subneg4

A variant is also possible with four operands – subneg4. The reversal of minuend and subtrahend eases implementation in hardware. The non-destructive result simplifies the synthetic instructions.

subneg4 s, m, r, j ; subtrahend, minuend, result and jump addresses
; Mem = Mem - Mem
; if goto j

Arithmetic machine

In an attempt to make Turing machine more intuitive, Z. A. Melzac consider the task of computing with positive numbers. The machine has an infinite abacus, an infinite number of counters initially at a special location S. The machine is able to do one operation:

Take from location X as many counters as there are in location Y and transfer them to location Z and proceed to next instruction.
If this operation is not possible because there is not enough counters in Y, then leave the abacus as it is and proceed to instruction T.

This essentially a subneg where the test is done before rather than after the subtraction, in order to keep all numbers positive and mimic a human operator computing on a real world abacus.
Pseudocode:

command X, Y, Z, T ; if goto T
; Mem = Mem - Mem

After giving a few programs: multiplication, gcd, computing the n-th prime number, representation in base b of an arbitrary number, sorting in order of magnitude, Melzac shows explicitly how to simulate an arbitrary Turing machine on his arithmetic machine.
He mentions that it can easily be shown using the elements of recursive functions that every number calculable on the arithmetic machine is computable. A proof of which was given by Lambek on an equivalent two instruction machine : X+ and X− else T.

Reverse subtract and skip if borrow

In a reverse subtract and skip if borrow instruction, the accumulator is subtracted from the memory location and the next instruction is skipped if there was a borrow. The result is stored in both the accumulator and the memory location. The program counter is mapped to memory location 0. The accumulator is mapped to memory location 1.

Example

To set x to the value of y minus z:

# First, move z to the destination location x.
RSSB temp # Three instructions required to clear acc, temp
RSSB temp
RSSB temp
RSSB x # Two instructions clear acc, x, since acc is already clear
RSSB x
RSSB y # Load y into acc: no borrow
RSSB temp # Store -y into acc, temp: always borrow and skip
RSSB temp # Skipped
RSSB x # Store y into x, acc
# Second, perform the operation.
RSSB temp # Three instructions required to clear acc, temp
RSSB temp
RSSB temp
RSSB z # Load z
RSSB x # x = y - z

If the value stored at "temp" is initially a negative value and the instruction that executed right before the first "RSSB temp" in this routine borrowed, then four "RSSB temp" instructions will be required for the routine to work.
If the value stored at "z" is initially a negative value then the final "RSSB x" will be skipped and thus the routine will not work.

Transport triggered architecture

A transport triggered architecture uses only the move instruction, hence it was originally called a "move machine". This instruction moves the contents of one memory location to another memory location combining with the current content of the new location:
move a to b ; Mem := Mem Mem
sometimes written as:
a -> b ; Mem := Mem Mem
The operation performed is defined by the destination memory cell. Some cells are specialized in addition, some other in multiplication, etc. So memory cells are not simple store but coupled with an arithmetic logic unit setup to perform only one sort of operation with the current value of the cell. Some of the cells are control flow instructions to alter the program execution with jumps, conditional execution, subroutines, if-then-else, for-loop, etc...
A commercial transport triggered architecture microcontroller has been produced called MAXQ, which hides the apparent inconvenience of an OISC by using a "transfer map" that represents all possible destinations for the move instructions.

Cryptoleq

Cryptoleq is a language consisting of one instruction, the eponymous, is capable of performing general-purpose computation on encrypted programs and is a close relative to Subleq. Cryptoleq works on continuous cells of memory using direct and indirect addressing, and performs two operations and on three values A, B, and C:
Cryptoleq a, b, c = O1 ;
IP = c, if O2 ≤ 0
IP = IP + 3, otherwise
where a, b and c are addressed by the instruction pointer, IP, with the value of IP addressing a, IP + 1 point to b and IP + 2 to c.
In Cryptoleq operations and are defined as follows:
The main difference with Subleq is that in Subleq, simply subtracts from and equals to. Cryptoleq is also homomorphic to Subleq, modular inversion and multiplication is homomorphic to subtraction and the operation of corresponds the Subleq test if the values were unencrypted. A program written in Subleq can run on a Cryptoleq machine, meaning backwards compatibility. Cryptoleq though, implements fully homomorphic calculations and since the model is be able to do multiplications. Multiplication on an encrypted domain is assisted by a unique function G that is assumed to be difficult to reverse engineer and allows re-encryption of a value based on the operation:
where is the re-encrypted value of and is encrypted zero. is the encrypted value of a variable, let it be, and equals.
The multiplication algorithm is based on addition and subtraction, uses the function G and does not have conditional jumps nor branches. Cryptoleq encryption is based on Paillier cryptosystem.