Microarchitecture simulation can be classified into multiple categories according to input types and level of details. Specifically, the input can be a trace collected from an execution of program on a real microprocessor or a program itself. A trace-driven simulation reads a fixed sequence of trace records from a file as an input. These trace records usually represent memory references, branch outcomes, or specific machine instructions, among others. While a trace-driven simulation is known to be comparatively fast and its results are highly reproducible, it also requires a very large storage space. On the other hand, an execution-driven simulation reads a program and simulates the execution of machine instructions on the fly. A program file is typically several magnitudes smaller than a trace file. However, the execution-driven simulation is much slower than the trace-driven simulation because it has to process each instruction one-by-one and update all statuses of the microarchitecture components involved. Thus, the selection of input types for simulation is a trade-off between space and time. In particular, a very detailed trace for a highly accurate simulation requires a very large storage space, whereas a very accurate execution-driven simulation takes a very long time to execute all instructions in the program. Apart from input types, the level of details can also be used to classify the simulation. In particular, a piece of software that simulates a microprocessor executing a program on a cycle-by-cycle basis is known as cycle-accurate simulator, whereas instruction set simulator only models the execution of a program on a microprocessor through the eyes of an instruction scheduler along with a coarse timing of instruction execution. Most computer science classes in computer architecture with hand-on experiences adopt the instruction set simulators as tools for teaching, whereas the cycle-accurate simulators are deployed mostly for research projects due to both complexities and resource consumption.
Usages
Microarchitecture simulators are deployed for a variety of purposes. It allows researchers to evaluate their ideas without the need to fabricate a real microprocessor chip, which is both expensive and time consuming. For instance, simulating a microprocessor with thousand of cores along with multiple levels of cache memory incurs very little cost when comparing with the fabrication of a prototyping chip. The researchers can also play with several configurations of the cache hierarchy using different cache models in the simulator instead of having to fabricate a new chip every time they want to test something different. Another usage of the microarchitecture simulator is in education. Given that a course in computer architecture teaches students many different microprocessor's features and its architectures, the microarchitecture simulator is ideal for modeling and experimenting with different features and architectures over the course of a semester. For example, students may start with a microarchitecture simulator that models a simple microprocessor designat the beginning of a semester. As the semester progresses, additional features, such as instruction pipelining, register renaming, reservation stations, out-of-order execution, and scoreboarding, can be modeled and added to the simulator as they are introduced in the classroom. Microarchitecture simulator provides the flexibility of reconfiguration and testing with minimal costs.
