Machine state register
A machine state register is one of three process control registers present in the PowerPC processor architecture.
Processors
The implementation details of the machine state register will vary from model to model. Below are two representative implementations, the 32-bit Freescale e200z3 PowerPC core and the 64-bit IBM PowerPC.e200z3 PowerPC core
Uses of the machine state register
This 32-bit register either controls and/or reports several important processor states.Mnemonic | Description |
UCLE | Enables/disables userspace execution of cache locking instructions |
SPE | Enables/disables vector instructions |
WE | Enables/disables power management |
CE | Enables/disables critical interrupts |
EE | Enables/disables external interrupts |
PR | Identifies if the processor is in supervisor or user mode |
FP | Identifies availability of hardware floating point unit |
ME | Enables/disables machine check interrupts |
FE0 | Sets floating point exception mode |
DE | Enable/disable debug interrupts |
FE1 | Sets floating point exception mode |
IS | Sets instruction address space |
DS | Sets data address space |
Reading and writing the machine state register
The contents of the register may be read using the move from machine state register instruction and may be modified by executing the return from interrupt, system call and move to machine state register instructions.PowerPC
Uses of the machine state register
This 64-bit register either controls and/or reports several important processor states.Mnemonic | Description |
SF | Selects 32-bit/64-bit mode |
HV | Selects hypervisor state |
EE | Enable/disable external interrupts |
PR | Selects privileged or problem state |
FP | Reports floating-point availability |
ME | Enables/disables machine check interrupts |
FE0 | Select floating-point mode exception mode |
SE | Enables/disables single-step tracing |
BE | Enables/disables branch tracing |
FE1 | Select floating-point exception mode |
IR | Enable/disable instruction address translation |
DR | Enable/disable data address translation |
PMM | Performance monitor mark |
RI | Lists whether interrupt is recoverable |
LE | Selects Little-Endian or Big-Endian mode |