Machine Check Architecture
In computing, Machine Check Architecture is an Intel mechanism in which the CPU reports hardware errors to the operating system.
Intel's Pentium 4, Intel Xeon, P6 family processors as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware errors, such as: system bus errors, ECC errors, parity errors, cache errors, and translation lookaside buffer errors. It consists of a set of model-specific registers that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected.
