Load–store architecture
In computer engineering, a load–store architecture is an instruction set architecture that divides instructions into two categories: memory access, and ALU operations.
RISC instruction set architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures.
For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a register–memory architecture in which one of the operands for the ADD operation may be in memory, while the other is in a register.
The earliest example of a load–store architecture was the CDC 6600. Almost all vector processors use the load–store approach.
