The Intel QuickPath Interconnect is a point-to-point processorinterconnect developed by Intel which replaced the front-side bus in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and available bandwidth. Prior to the name's announcement, Intel referred to it as Common System Interface. Earlier incarnations were known as Yet Another Protocol and YAP+. QPI 1.1 is a significantly revamped version introduced with Sandy Bridge-EP. QPI was replaced by Intel Ultra Path Interconnect in Skylake-SP Xeon processors based on LGA 3647 socket.
Background
Although sometimes called a "bus", QPI is a point-to-point interconnect. It was designed to compete with HyperTransport that had been used by Advanced Micro Devices since around 2003. Intel developed QPI at its Massachusetts Microprocessor Design Center by members of what had been the Alpha Development Group, which Intel had acquired from Compaq and HP and in turn originally came from Digital Equipment Corporation. Its development had been reported as early as 2004. Intel first delivered it for desktop processors in November 2008 on the Intel Core i7-9xx and X58chipset. It was released in Xeon processors code-named Nehalem in March 2009 and Itanium processors in February 2010.
Implementation
The QPI is an element of a system architecture that Intel calls the QuickPath architecture that implements what Intel calls QuickPath technology. In its simplest form on a single-processor motherboard, a single QPI is used to connect the processor to the IO Hub. In more complex instances of the architecture, separate QPI link pairs connect one or more processors and one or more IO hubs or routing hubs in a network on the motherboard, allowing all of the components to access other components via the network. As with HyperTransport, the QuickPath Architecture assumes that the processors will have integrated memory controllers, and enables a non-uniform memory access architecture. Each QPI comprises two 20-lane point-to-point data links, one in each direction, with a separate clock pair in each direction, for a total of 42 signals. Each signal is a differential pair, so the total number of pins is 84. The 20 data lanes are divided onto four "quadrants" of 5 lanes each. The basic unit of transfer is the 80-bit flit, which is transferred in two clock cycles The 80-bit flit has 8 bits for error detection, 8 bits for "link-layer header", and 64 bits for data. QPI bandwidths are advertised by computing the transfer of 64 bits of data every two clock cycles in each direction. Although the initial implementations use single four-quadrant links, the QPI specification permits other implementations. Each quadrant can be used independently. On high-reliability servers, a QPI link can operate in a degraded mode. If one or more of the 20+1 signals fails, the interface will operate using 10+1 or even 5+1 remaining signals, even reassigning the clock to a data signal if the clock fails. The initial Nehalem implementation used a full four-quadrant interface to achieve 25.6 GB/s, which provides exactly double the theoretical bandwidth of Intel's 1600 MHz FSB used in the X48 chipset. Although some high-end Core i7 processors expose QPI, other "mainstream" Nehalem desktop and mobile processors intended for single-socket boards do not expose QPI externally, because these processors are not intended to participate in multi-socket systems. However, QPI is used internally on these chips to communicate with the "uncore", which is part of the chip containing memory controllers, CPU-side PCI Express and GPU, if present; the uncore may or may not be on the same die as the CPU core, for instance it is on a separate die in the Westmere-based Clarkdale/Arrandale. These post-2009 single-socket chips communicate externally via the slower DMI and PCI Express interfaces, because the functions of the traditional northbridge are actually integrated into these processors, starting with Lynnfield, Clarksfield, Clarkdale and Arrandale; thus, there is no need to incur the expense of exposing the front-side bus interface via the processor socket. Although the core–uncore QPI link is not present in desktop and mobile Sandy Bridge processors, the internal ring interconnect between on-die cores is also based on the principles behind QPI, at least as far as cache coherency is concerned.
Frequency specifications
QPI operates at a clock rate of 2.4 GHz, 2.93 GHz, 3.2 GHz, 3.6 GHz, 4.0 GHz or 4.8 GHz. The clock rate for a particular link depends on the capabilities of the components at each end of the link and the signal characteristics of the signal path on the printed circuit board. The non-extreme Core i7 9xx processors are restricted to a 2.4 GHz frequency at stock reference clocks. Bit transfers occur on both the rising and the falling edges of the clock, so the transfer rate is double the clock rate. Intel describes the data throughput by counting only the 64-bit data payload in each 80-bit flit. However, Intel then doubles the result because the unidirectional send and receive link pair can be simultaneously active. Thus, Intel describes a 20-lane QPI link pair with a 3.2 GHz clock as having a data rate of 25.6 GB/s. A clock rate of 2.4 GHz yields a data rate of 19.2 GB/s. More generally, by this definition a two-link 20-lane QPI transfers eight bytes per clock cycle, four in each direction. The rate is computed as follows:
Protocol layers
QPI is specified as a five-layer architecture, with separate physical, link, routing, transport, and protocol layers. In devices intended only for point-to-point QPI use with no forwarding, such as the Core i7-9xx and Xeon DP processors, the transport layer is not present and the routing layer is minimal. ; Physical layer ; Link layer ; Routing layer ; Transport layer ; Protocol layer
