Epyc is a brand of x86-64microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets. Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. They also support multi-chip and dual-socket system configurations by using Infinity Fabric interchip interconnect.
History
In March 2017, AMD announced a server platform based on the Zen microarchitecture, codenamed Naples, and officially revealed it under the brand name Epyc in May. That June, AMD officially launched Epyc by releasing the Epyc 7001 series processors. Two years later, in August 2019, the Epyc 7002 series processors based on the Zen 2 microarchitecture released, bringing much better performance and double the cores compared to their predecessors. The futureZen 3 based Epyc microarchitecture will be codenamed "Milan".
The platform includes one- and two-socket systems. In multi-processor configurations, two Epyc CPUs communicate via AMD's Infinity Fabric. Each server chip supports 8 channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes from each are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration. All Epyc processors are composed of four eight-core Zeppelin dies in a multi-chip module, with the varying product core counts produced by symmetrically disabling cores of each core complex on each Zeppelin die. Unlike Opteron, Intel equivalents and AMD's desktop processors, Epyc processors are chipset-free - also known as system on a chip. That means most features required to make servers fully functional are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some unavailable features require additional controller chips to make them available on the system. The first generation of Epyc microprocessors were manufactured by GlobalFoundries using a 14 nm FinFETprocess licensed from Samsung Electronics. Epyc 2 will be manufactured by TSMC using a 7 nm FinFET process.
Reception
Initial reception to Epyc was generally positive. Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in high-performance computing and big-data applications. First generation Epyc fell behind in database tasks compared to Intel's Xeon parts due to higher cache latency.
Features
Products
Server
First generation Epyc (Naples)
The following table lists the devices using the first generation design. A "P" suffix denotes support for only a single socket configuration. Non-P models use 64 PCI-E lanes from each processor for the communication between processors.
In November 2018 AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors code-named "Rome" and based on the Zen 2 microarchitecture. The processors feature up to eight 7nm-based "chiplet" processors with a 14 nm-based IO chip in the center interconnected via Infinity Fabric. The processors support up to 8 channels of DDR4 RAM up to 4 TB, and introduce support for PCIe 4.0. These processors have up to 64 cores with 128 SMT threads per socket. The 7nm "Rome" is manufactured by TSMC. It was released on August 7, 2019.
At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the Zen 3 microarchitecture. Milan chips will use Socket SP3, with up to 64 cores on die, and support eight DDR4 SDRAM and PCIe 4.0 channels. It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the Zen 4 microarchitecture and use Socket SP5.
A variant created for the Chinese server market by an AMD–Chinese joint venture is the Hygon Dhyana system on a chip. It is noted to be a variant of the AMD EPYC, and is so similar that "there is little to no differentiation between the chips". It has been noted that there is "less than 200 lines of new kernel code" for Linux kernel support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market". Later Benchmarks showed that certain floating point instructions are performing worse and AES is disabled, probably to comply with US export restrictions.
