Comparison of instruction set architectures
An instruction set architecture is an abstract model of a computer. It is also referred to as architecture or computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost ; because the ISA serves as the interface between software and hardware. Software that has been written for an ISA can run on different implementations of the same ISA. This has enabled binary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in computing today.
An ISA defines everything a machine language programmer needs to know in order to program a computer. What an ISA defines differs between ISAs; in general, ISAs define the supported data types, what state there is and their semantics, the instruction set, and the input/output model.
Base
In the early decades of computing, there were computers that used binary, decimal and even ternary. Contemporary computers are almost exclusively binary.Bits
s are often described as n-bit architectures. Today n is often 8, 16, 32, or 64, but other sizes have been used. This is actually a strong simplification. A computer architecture often has a few more or less "natural" datasizes in the instruction set, but the hardware implementation of these may be very different. Many architectures have instructions operating on half and/or twice the size of respective processors' major internal datapaths. Examples of this are the 8080, Z80, MC68000 as well as many others. On this type of implementations, a twice as wide operation typically also takes around twice as many clock cycles. On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The external databus width is often not useful to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses. The NS32764 had a 64-bit bus, but used 32-bit registers.The width of addresses may or may not be different from the width of data.
Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.
Operands
The number of operands is one of the factors that may give an indication about the performance of the instruction set.A three-operand architecture will allow
A := B + C
to be computed in one instruction.
A two-operand architecture will allow
A := A + B
to be computed in one instruction, so two instructions will need to be executed to simulate a single three-operand instruction
A := B
A := A + C
Endianness
An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big endian architectures instead order them with the most significant byte at the lowest-numbered address. The x86 architecture as well as several 8-bit architectures are little endian. Most RISC architectures were originally big endian, but many are now configurable.Endianness only applies to processors that allow individual addressing of units of data that are smaller than the basic addressable machine word.
Instruction sets
Usually the number of registers is a power of two, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" of register files of architectures, mostly to simplify indexing modes. This table only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program pointer. Those are not counted unless mentioned. Note that some architectures, such as SPARC, have register window; for those architectures, the count below indicates how many registers are available within a register window. Also, non-architected registers for register renaming are not counted.Note, a common type of architecture, "load-store", is a synonym for "Register Register" below, meaning no instructions access memory except special – load to register – and store from register – with the possible exceptions of atomic memory operations for locking.
The table below compares basic information about instruction sets to be implemented in the CPU architectures:
| Archi- tecture | Bits | Version | Intro- duced | Max # operands | Type | Design | Registers | Instruction encoding | Branch evaluation | Endian- ness | Extensions | Open | Royalty free |
| 6502 | 8 | 1975 | 1 | Register Memory | CISC | 3 | Variable | Condition register | Little | ||||
| 6809 | 8 | 1978 | 1 | Register Memory | CISC | 9 | Variable | Condition register | Big | ||||
| 680x0 | 32 | 1979 | 2 | Register Memory | CISC | 8 data and 8 address | Variable | Condition register | Big | ||||
| 8080 | 8 | 1974 | 2 | Register Memory | CISC | 8 | Variable | Condition register | Little | ||||
| 8051 | 32 | 1977? | 1 | Register Register | CISC | Variable | Compare and branch | Little | |||||
| x86 | 16, 32, 64 | 1978 | 2 3 4 | Register Memory | CISC | Variable | Condition code | Little | x87, IA-32, MMX, 3DNow!, SSE, SSE2, PAE, x86-64, SSE3, SSSE3, SSE4, BMI, AVX, AES, FMA, XOP, F16C | ||||
| Alpha | 64 | 1992 | 3 | Register Register | RISC | 32 | Fixed | Condition register | Bi | ,,, | |||
| ARC | 16/32 | ARCv2 | 1996 | 3 | Register Register | RISC | 16 or 32 including SP user can increase to 60 | Variable | Compare and branch | Bi | APEX User-defined instructions | ||
| ARM/A32 | 32 | ARMv1-v8 | 1983 | 3 | Register Register | RISC | Fixed | Condition code | Bi | NEON, Jazelle,, TrustZone, | |||
| Thumb/T32 | 32 | ARMv4T-ARMv8 | 1994 | 3 | Register Register | RISC | Thumb: Fixed, Thumb-2: Variable | Condition code | Bi | NEON, Jazelle,, TrustZone, | |||
| Arm64/A64 | 64 | ARMv8-A | 2011 | 3 | Register Register | RISC | 32 | Fixed | Condition code | Bi | none: all ARMv7 extensions are non-optional | ||
| AVR | 8 | 1997 | 2 | Register Register | RISC | 32 16 on "reduced architecture" | Variable | Condition register, skip conditioned on an I/O or general purpose register bit, compare and skip | Little | ||||
| AVR32 | 32 | Rev 2 | 2006 | 2–3 | RISC | 15 | Variable | Big | Java Virtual Machine | ||||
| Blackfin | 32 | 2000 | 3 | Register Register | RISC | 2 accumulators 8 data registers 8 pointer registers 4 index registers 4 buffer registers | Variable | Condition code | Little | ||||
| CDC 6000 | 60 | 1964 | 3 | Register Memory | RISC | 24 | Variable | Compare and branch | n/a | Compare/Move Unit, additional Peripheral Processing Units | |||
| Crusoe | 32 | 2000 | 1 | Register Register | VLIW | Variable | Condition code | Little | |||||
| Elbrus | 64 | Elbrus-4S | 2014 | 1 | Register Register | VLIW | 8–64 | 64 | Condition code | Little | Just-in-time dynamic trans- lation: x87, IA-32, MMX, SSE, SSE2, x86-64, SSE3, AVX | ||
| DLX | 32 | 1990 | 3 | RISC | 32 | Fixed | Big | ||||||
| eSi-RISC | 16/32 | 2009 | 3 | Register Register | RISC | 8–72 | Variable | Compare and branch and condition register | Bi | User-defined instructions | |||
| Itanium | 64 | 2001 | Register Register | EPIC | 128 | Fixed | Condition register | Bi | Intel Virtualization Technology | ||||
| M32R | 32 | 1997 | 3 | Register Register | RISC | 16 | Variable | Condition register | Bi | ||||
| Mico32 | 32 | 2006 | 3 | Register Register | RISC | 32 | Fixed | Compare and branch | Big | User-defined instructions | |||
| MIPS | 64 | 6 | 1981 | 1–3 | Register Register | RISC | 4–32 | Fixed | Condition register | Bi | MDMX, MIPS-3D | ||
| MMIX | 64 | 1999 | 3 | Register Register | RISC | 256 | Fixed | Big | |||||
| NS320xx | 32 | 1982 | 5 | Memory Memory | CISC | 8 | Variable Huffman coded, up to 23 bytes long | Condition code | Little | BitBlt instructions | |||
| OpenRISC | 32, 64 | 1.3 | 2010 | 3 | Register Register | RISC | 16 or 32 | Fixed | |||||
| PA-RISC | 64 | 2.0 | 1986 | 3 | Register Register | RISC | 32 | Fixed | Compare and branch | Big → Bi | MAX | ||
| PDP-8 | 12 | 1966 | Register Memory | CISC | 1 accumulator 1 multiplier quotient register | Fixed | Condition register Test and branch | EAE | |||||
| PDP-11 | 16 | 1970 | 3 | Memory Memory | CISC | 8 | Fixed | Condition code | Little | Floating Point, Commercial Instruction Set | |||
| POWER, PowerPC, Power ISA | 32/64 | 3.0B | 1990 | 3 | Register Register | RISC | 32 | Fixed, Variable | Condition code | Big/Bi | AltiVec, APU, VSX, Cell | ||
| RISC-V | 32, 64, 128 | 2.2 | 2010 | 3 | Register Register | RISC | 32 | Variable | Compare and branch | Little | |||
| RX | 64/32/16 | 2000 | 3 | Memory Memory | CISC | 4 integer + 4 address | Variable | Compare and branch | Little | ||||
| S+core | 16/32 | 2005 | RISC | Little | |||||||||
| SPARC | 64 | OSA2017 | 1985 | 3 | Register Register | RISC | 32 | Fixed | Condition code | Big → Bi | VIS | ||
| SuperH | 32 | 1994 | 2 | Register Register Register Memory | RISC | 16 | Fixed, Variable | Condition code | Bi | ||||
| System/360 System/370 z/Architecture | 64 | 1964 | 2 3 4 | Register Memory Memory Memory Register Register | CISC | 16 | Variable | Condition code, compare and branch | Big | ||||
| Transputer | 32 | 1987 | 1 | Stack machine | MISC | 3 | Variable | Compare and branch | Little | ||||
| VAX | 32 | 1977 | 6 | Memory Memory | CISC | 16 | Variable | Compare and branch | Little | ||||
| Z80 | 8 | 1976 | 2 | Register Memory | CISC | 17 | Variable | Condition register | Little | ||||
| Archi- tecture | Bits | Version | Intro- duced | Max # operands | Type | Design | Registers | Instruction encoding | Branch evaluation | Endian- ness | Extensions | Open | Royalty free |