3 nm process


In semiconductor manufacturing, the 3 nm process is the next die shrink after the 5-nanometre MOSFET technology node. As of 2019, Samsung and TSMC have announced plans to put a 3 nm semiconductor node into commercial production. It is based on GAAFET technology, a type of multi-gate MOSFET technology.

History

Research and technology demos

In 1985, a Nippon Telegraph and Telephone research team fabricated a MOSFET device with a channel length of 150 nm and gate oxide thickness of 2.5 nm. In 1998, an Advanced Micro Devices research team fabricated a MOSFET device with a channel length of 50 nm and oxide thickness of 1.3 nm.
In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes. In 2006, a team from the Korea Advanced Institute of Science and Technology and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around technology.

Commercialization history

In late 2016, TSMC announced plans to construct a 5 nm–3 nm node semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion.
In 2017, TSMC announced it was to begin construction of the 3 nm semiconductor fabrication plant at the Tainan Science Park in Taiwan. TSMC plans to start volume production of the 3 nm process node in 2023.
In early 2018, IMEC and Cadence stated they had taped out 3 nm test chips, using extreme ultraviolet lithography and 193 nm immersion lithography.
In early 2019, Samsung presented plans to manufacture 3 nm GAAFET at the 3 nm node in 2021; Samsung's semiconductor roadmap also included products at 8, 7, 6, 5, and 4 nm 'nodes'.
In December 2019, Intel announced plans for 3 nm production in 2025.
In January 2020, Samsung announced the production of the world's first 3 nm GAAFET process prototype, and said that it is targeting mass production in 2021.

Beyond 3 nm

The ITRS uses the terms "2.1 nm", "1.5 nm", and "1.0 nm" as generic terms for the nodes after 3 nm. "2-nanometre" and "14 angstrom" nodes have also been tentatively identified by An Steegen as future production nodes after 3 nm, with hypothesized introduction dates of around 2024, and beyond 2025 respectively.
In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes; however, as of 2019 other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable. TSMC began research on 2nm in 2019.
In December 2019, Intel announced plans for 1.4 nm production in 2029.