Prototypes using 32 nm technology first emerged in the mid-2000s, following the development of pitch double patterning by Gurtej Singh Sandhu at Micron Technology, which led to the development of NAND flash memory below 40nm. In 2004, IBM demonstrated a 0.143 μm2SRAM cell with a poly gate pitch of 135 nm, produced using electron-beam lithography and photolithography on the same layer. It was observed that the cell's sensitivity to input voltage fluctuations degraded significantly at such a small scale. In October 2006, the Interuniversity Microelectronics Centre demonstrated a 32 nm flash patterning capability based on double patterning and immersion lithography. The necessity of introducing double patterning and hyper-NA tools to reduce memory cell area offset some of the cost advantages of moving to this node from the 45 nm node. TSMC similarly used double patterning combined with immersion lithography to produce a 32 nm node 0.183 μm2 six-transistor SRAM cell in 2005. Intel Corporation revealed its first 32 nm test chips to the public on 18 September 2007 at the Intel Developer Forum. The test chips had a cell size of 0.182 μm2, used a second-generation high-κ gate dielectric and metal gate, and contained almost two billion transistors. 193 nm immersion lithography was used for the critical layers, while 193 nm or 248 nm dry lithography was used on less critical layers. The critical pitch was 112.5 nm. In January 2011, Samsung completed development of the industry's first DDR4SDRAM module using a process technology with a size between 30 nm and 39 nm. The module could reportedly achieve data transfer rates of 2.133 Gbit/s at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent 30 nm-class process technology with speeds of up to 1.6 Gbit/s. The module used pseudo open drain technology, specially adapted to allow DDR4 SDRAM to consume just half the current of DDR3 when reading and writing data.
Processors using 32 nm technology
Intel's Core i3 and i5 processors, released in January 2010, were among the first mass-produced processors to use 32 nm technology. Intel's second-generation Core processors, codenamed Sandy Bridge, also used the 32 nm manufacturing process. Intel's 6-core processor, codenamed Gulftown and built on the Westmere architecture, was released on 16 March 2010 as the Core i7 980x Extreme Edition, retailing for approximately US$1,000. Intel's lower-end 6-core, the i7-970, was released in late July 2010, priced at approximately US$900. AMD also released 32 nm SOI processors in the early 2010s. AMD's FX Series processors, codenamed Zambezi and based on AMD's Bulldozer architecture, were released in October 2011. The technology utilised a 32 nm SOI process, two CPU cores per module, and up to four modules, ranging from a quad-core design costing approximately US$130 to a $280 eight-core design. In September 2011, Ambarella Inc. announced the availability of the 32 nm-based A7L system-on-a-chip circuit for digital still cameras, providing 1080p60 high-definition video capabilities.
Successor node
The successor to 32 nm technology was the 22 nm node, per the International Technology Roadmap for Semiconductors. Intel began mass production of 22 nm semiconductors in late 2011, and announced the release of its first commercial 22 nm devices in April 2012. TSMC bypassed 32nm, jumping from 40nm in 2008 to 28nm in 2011.
